Hardware Modeling and Veri cation of an ATM Ring MAC Protocol

The VLSI design of nite-state concurrent hardware systems is toda ypresent in many elds, in particular in the design of digital and communication systems. Late detection of design errors in the design phase are very costly in any system development. These errors can delay the product deployment and even cause the failure of the product. The traditionally used simulation techniques cannot cover all design errors when the state space of the system is big. During the past years, model checking techniques [7] have established themselves as signi cant means for early detection of hardware design errors due to their abilit y of validation and conformance checking. Generally, when a protocol is implemented in VLSI, it is diÆcult to be handled by a soft w are (protocol) v eri cation tool. The latter ones are based on an in terlea ving model and cannot re ect the synchronous concurrency aspects of a hardware implementation. The aim of this paper is to describe the modeling and formal veri cation in VIS (Veri cation Interacting with Synthesis) [1] of the RTL hardware implementation of a single A TMring (ATMR) MAC protocol [3]. A number of related work can be found in the open literature. These can be classi ed in three major categories: (1) formal veri cation of high layer softw are protocols [5]; (2) formal v eri cation of synchronous hardware protocol [8]; and (3) formal veri cation of A TMhardware devices [6]. Our w orkdistinguishes itself from these related publications by the fact that we verify the V erilog RTL hardware implementation of an asynchronous MAC. We present some techniques on how to simulate the asynchronous ATMR MAC design in a sync hronous environment and also propose some abstraction and reduction approaches for the aimed veri cation. F urthermore, we analyze the performance of the source of the complexity in the veri cation with repsect to the CPU time, memory usage and state space. The rest of the paper is structured as follows. The next section introduces the ATMR MAC to be veri ed. Section 3 discusses the modeling techniques we used for the asynchronous MAC. Section 4 describes the veri cation of the asynchronous and synchronous MAC hardware implementation against a set of CTL consistency properties. Section 5 nally concludes the paper.